Digital communication systems enable telecommunication service providers (for example, a competitive local exchange carrier (CLEC), such as an internet service provider (ISP)), to provide various types of high speed digital service over network circuits of an incumbent local exchange carrier (ILEC), such as a Bell operating company (RBOC), serving a number of customer premises equipments (CPEs) having a wide range of operational bandwidths and digital subscriber line termination capabilities. A reduced complexity example of such a digital communication network architecture is diagrammatically illustrated in FIG. 1 as comprising a PCM communication link (such as an optical fiber) 10, through which a network (cloud) 20 at a ‘west’ end of the link 10 may transmit and receive digital telecommunication signals (e.g., packetized T3 traffic) with respect to customer premises equipments (CPEs) served by a remote termination site (RTS) 30 at an ‘east’ end of the PCM link 10.
As shown in FIG. 2, in order to handle transmission requests from the virtual circuits (VCs) that are associated with various customer equipments (CPEs), the equipment shelf of a remote terminal 30 terminating the ‘east’ end of the PCM link 10 typically contains a supervisory communication control processor 40, one of the functions of which is to arbitrate/grant the interfacing of packets awaiting transmission from one or more virtual circuit ports PVC1–PVCN to the PCM serial link 10. Now although a maximal speed/memory processor architecture could be used to execute a sequential polling scheme to accomplish this task, doing so would not only be cost-prohibitive from a commercial application standpoint, but could be expected to be a less than efficient use of available bandwidth (e.g., checking each and every virtual circuit port including those having no data to transmit).